Low-complexity, energy-efficient fully parallel split-radix FFT architecture

Fully parallel pipelined fast Fourier transform offers the highest throughput but requires high area and power. In this work, an efficient fast Fourier transform processor based on the split-radix algorithm is presented to reduce the hardware complexity of fully parallel fast Fourier transforms. In fully parallel pipelined implementations, split-radix fast Fourier transform requires considerably more registers compared to other fast Fourier transform algorithms leading to more power consumption and high latency in spite of having the least number of multiplications among all fast Fourier transforms. To address this issue, the authors present a new data-flow graph with no non-trivial twiddle factors in the odd stages of the split-radix fast Fourier transform. This facilitates significant reduction in the number of pipelining registers and a lower latency is achieved. Further, an efficient shift-add twiddle factor multiplier is proposed based on architectural analysis and substructure sharing. A comparison of the proposed design with existing fully parallel fast Fourier transforms is carried out and it is found that the proposed method outperforms other designs. Synthesis results show that the proposed design offers 45-57% area savings and 67-74% energy savings compared to the best existing fully parallel fast Fourier transform design.