Compact Word-Serial Modular Multiplier Accelerator Structure for Cryptographic Processors in IoT Edge Nodes with Limited Resources

IoT is extensively used in many infrastructure applications, including telehealth, smart homes, smart grids, and smart cities. However, IoT has the weakest link in system security since it often has low processing and power resources. It is important to implement the necessary cryptographic primitives in these devices using extremely efficient finite field hardware structures. Modular multiplication is the core of cryptographic operators. Therefore, we present, in this work, a word-serial modular multiplier accelerator structure that provides the system designer with the ability to manage areas, delays, and energy consumption through selecting the appropriate embedded processor word size l. The modularity and regularity of the suggested multiplier structure makes it more suitable for implementation in ASIC technology. The ASIC implementation results indicates that the offered multiplier structure achieves area reduction compared to the competitive existing multiplier structures that vary from 76.2% to 98.5% for l=8, from 73.1% to 98.1% for l=16, and from 82.9% to 98.3% for l=32. Moreover, the energy reduction varies from 61.2% to 98.8% for l=8, from 67.7% to 98.3% for l=16, and from 76.1% to 98.8% for l=32. These results indicate that the proposed modular multiplier structure significantly outperforms the competitive ones, in terms of area and consumed energy, making it more suitable for utilization in resource-constrained IoT edge devices.