High-resistivity silicon-based substrate using buried PN junctions towards RFSOI applications

•This paper shows the potential of buried PN junctions as a substrate interface passivation solution to increase the effective resistivity (ρeff) figure of merit of a High-Resistivity (HR) substrate suffering from Parasitic Surface Conduction layer (PSC).•We demonstrate that this method can be implemented using an industrial process with an effective resistivity reaching 2 kΩ.cm with 0.1 dB/mm loss at 6 GHz for a HR + PN substrate.•Temperature, dose and implantation energy variations were performed in order to identify the buried PN junctions robustness. At high-temperature, HR + PN substrate still shows an enhancement of RF performance.