Measuring the effect of track count and wire segment length on the layout area of switch blocks for tile-based FPGAs

Switch block flexibility is an important design metric in FPGA architectural research. A switch block with high flexibility can provide better routability for implementing digital applications, which can lead to better performance and logic density. Flexibility, however, does come at the cost of an increase in the layout area of switch blocks, which can lower performance and logic density. Consequently, it is important to accurately estimate the layout area of increasing switch block flexibility in order to better design FPGA architectures. This work focuses on the popular disjoint switch block design and evaluates the accuracy of the traditional active-based area estimation models based on realistic layouts. We found that the current active-based area models are inaccurate in estimating the true area cost of increasing switch block flexibility. This inaccuracy is due to the inability of the current models to consider the full effect of routing track count and wire segment length, two important flexibility parameters, on the layout area of switch blocks. We found that by including wiring area into the estimation of FPGA switch block layout area, one can significantly improve the accuracy of predicting the true area cost of these flexibility parameters. These results allow FPGA architects to better optimize future FPGA designs for routability and consequently for performance and logic density.