Development and Analysis of Novel Mesh of Tree-based embedded FPGA

The eFPGA IPs are made up of logic components connected by a routing network. The target architecture is a key feature of eFPGA development. There have been two main families of architecture: matrix and hierarchical topologies. The mesh architecture is distinguished by its genericity and regularity, but approximately 90% of the area is used by the routing network and just 10% by the logic blocks. Hierarchical architecture reduces this effect by on average 56% but increases the size of the critical path and causes the scalability problem. The architecture proposed in this paper will mix the benefits of the two existing architectures. This paper, therefore, proposes a Mesh of Tree architecture that maintains a strong balance between area density and layout scalability. To the best of our knowledge, this is the first eFPGA circuit with a mixing matrix and hierarchical architectures in a new eFPGA architecture. We compared the proposed eFPGA by Tree-based and Mesh of Cluster eFPGA in terms of area, power dissipation, performance and frequency. Mesh of Tree eFPGA imposes an area overhead but has a straightforward advantage in terms of performance for architectures with a size greater than 64 LUTs. The results of the experiments demonstrate that the proposed Mesh of Tree architecture has strong physical scalability: Once the layout of the nodes is generated, it can be used to create matrix layouts of the target size and shape factor.