Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications

With technology scaling, transistor sizing as well as the distance between them, is decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction makes SRAM cells used for aerospace applications more susceptible to radiation as it can cause single-event upsets (SEUs) and also single-event multi-node upsets (SEMNUs). This article presents an energy-efficient dual-node-upset recoverable 12T SRAM cell for low-power aerospace applications, EDP12T, in 65-nm CMOS technology. The proposed cell mitigates SEUs as well as SEMNUs. To judge the relative performance of EDP12T, a comparative study is made between it and other radiation-hardened cells: RHM12T, QUCCE12T, QUATRO12T, RHD12T, SRRD12T, RHPD12T, RSP14T, LWS14T, SAR14T, and S8P4N16T. EDP12T can recover from SEUs induced at all the sensitive nodes and from SEMNUs that have occurred at its internal node-pair. EDP12T exhibits better write performance than most of the comparison cells, it also consumes the least energy during write mode, and lower energy than most of the comparison cells during read mode. EDP12T exhibits a 1.08x/1.17x/1.37x/1.56x/2.32x higher read stability than S8P4N16T/RHPD12T/QUCCE12T/QUATRO12T/LWS14T. Additionally, EDP12T dissipates the lowest hold power among all the cells for comparison, except for RHM12T. These improvements are obtained by the proposed cell while consuming a 1.03x/1.06x/1.07x/1.08x/1.14x/1.43x/2.01x lower area than SAR14T/RHD12T/S8P4N16T/RSP14T/LWS14T/RHPD12T/SRRD12T. However, these advantages come with a slight penalty in the read delay.