A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator

This brief presents a low-power asynchronous 10-bit 2-then-1b/cycle successive approximation register (SAR) analog-to-digital converter (ADC). With partial adoption of 2b/cycle mode only for higher-order bit conversions, additional area and power consumption could be minimized while maintaining fast conversion rate. Moreover, unlike the previous 2b/cycle conversion architecture, where two capaciti...