Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

In this work, the effect of gate misalignment towards the source and drain ends for 20 nm recessed double gate junctionless field-effect-transistor (R_DGJLFET) have been studied on various digital and analog performance parameters from device to circuit level while setting the simulation set-up using 2D Silvaco ATLAS technology computer aided design (TCAD). With recessed silicon channel, the quantum confinement effects have been considered for channel thickness <7 nm. In comparison to conventional double gate junctionless FET (C_DGJLFET), the device exhibits lesser OFF-current, improved ON-to-OFF current ratio, better subthreshold slope (SS), and lower drain-induced-barrier-lowering (DIBL). Analogically, it has been found that the misaligned gate towards drain affects the digital and analog parameters more severely in comparison to gate misalignment towards the source end. However, the misaligned R_DGJLFET towards the drain end shows robustness in terms of SS and DIBL with smaller variations of similar to 10.84% and similar to 61.79%, respectively. Moreover, due to very low parasitic capacitances, the device shows lesser variations in different alternating current (AC) performance parameters namely, transconductance generation factor (TGF), unity gain frequency, and gain-bandwidth product in comparison to C_DGJLFET. With gate misalignment towards source the unity gain frequency, and gain-bandwidth improve by similar to 9.67% and similar to 19.9%, respectively whereas the TGF remains almost unaffected. Furthermore, to ensure the device capability in circuit application a complementary metal-oxide-semiconductor (CMOS) inverter and common-source (CS) amplifier based on R_DGJLFET have been designed. In contrast to C_DGJLFET based counterpart, the R_DGJLFET expresses its suitability for low-power digital applications with better noise margins and smaller short-circuit current in the CMOS inverter. In analog domain, the R_DGJLFET based CS amplifier shows an improved amplification factor of 4.75 in comparison to C_DGJLFET. This paper provides deep insight into the severity of gate misalignment towards source/drain for R_DGJLFET in both digital and analog domains from device to circuit level.