Process Dependent Material Characterization for Warpage Control of Fan-Out Wafer Level Packaging

Fan-out Wafer-Level Packaging (FO-WLP) is seen as an enabling technology for new packaging options in heterogeneous integration. For the RDL-last approach the chips are embedded in a mold process on a carrier and the electrical connection is realized with redistribution layers (RDL) in a wafer level process, which enables high precision interconnects. A major challenge within this process is to control the warpage of the molded wafer. As in future a multitude of different package types and applications are being addressed, this warpage control needs to be realized for different materials, process conditions and package designs. Therefore, a precise simulation technology becomes necessary to assess the influence of different design features on warpage. This paper focusses on the analysis of warpage behavior throughout the first crucial process steps. An example mold material is comprehensively analyzed in order to identify crucial steps in the planned modelling approach. The analysis covers the temperatures and times applied in post mold cure (150 degrees C), thermal release (200 degrees C) and RDL cure (250 degrees C) with a special focus on 200 degrees C. The warpage is measured on a sample combining mold and a silicon wafer with a diameter of 200 mm. Throughout these steps, the development of warpage is quantified and it is shown that an irreversible warpage behavior (hysteresis) is highly relevant. With the combination of thermomechanical measurements (TMA, DMA) and finite element modelling the origin of this effect is being identified. Thus a new approach is suggested to characterize and model warpage in processing of molded wafers at elevated temperatures and a basis is given to control warpage and improve the prediction capability of finite element models.