Design and Analysis of a Multi Clocked Pipelined Processor Based on RISC-V

Sandeep Prabhakaran,Mathan N,V Vedanarayanan

2022 International Conference on Communication, Computing and Internet of Things (IC3IoT)（2022）

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摘要

The main goal of this study is to develop a 32-bit pipelined processor with several clock domains based on the RISC-V (open source RV32I Version 2.0) ISA. To minimise the complexity of the instruction set and speed up the execution time per instruction, RISC (Reduced Instruction Set Computer) is a type of processor that uses less hardware than CISC (Complex Instruction Set Computer) is used. Furth...

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关键词

Reduced instruction set computing,Computational modeling,Throughput,Delays,Telecommunication computing,Registers,Internet of Things

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