Optimizing Finite Impulse Response Filter Design

In this study, we explored a potential design for a 64-tap 16-bit Finite Impulse Response (FIR) Filter, including several optimizations. We used RTL code, synthesized gate-level netlist, and ran PrimeTime analysis for each component and the overall circuit. We present the methodology associated with this approach, and its operational results. The design chosen uses a 16-bit floating point ALU with a dual-clock, first in first out memory architecture. The final FIR core was functional, as measured via timing and power analysis, throughput, maximum clock frequency, area, error rate, and accuracy.