Fault Tolerant Adders With Low Overheads For Smart Computing

In this paper the authors analyse different adder designs with respect to the extent of fault. If the fault is localized the fault free part of the tree may be brought in use thereby improving the throughput. The results indicate the suitability of Ling parallel prefix adders for implementation of fault tolerant adders due to the fact that the fault effects the even or odd part of the tree and leaves the odd or even part fault free. A design for online error detection is proposed employing the Ling parallel prefix adders as the adjacent columns compute independently. Then the design is used in the implementation of the 15–4 compressor of a Wallace Tree Multiplier so that it has the capacity to detect faults. Further, a Ling parallel prefix adder with fault tolerance is designed to augment the online error detection design. This is compared with the existing designs and it shows an improvement in delay of about 30% compared to RCA-TMR scheme and 50% when compared to the traditional Prefix adders with fault tolerance. There is a significant improvement in ADP & PDP values. Finally, a scheme to mitigate overheads using approximate computation is proposed.