A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion

Shao-Yu Shu,Chun-Hung Lin,Ching-Yuan Yang

2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)（2022）

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摘要

In this paper, a 5-GHz frequency synthesizer based on sub-sampling phased locked loop (SSPLL) using a pulse-width to current conversion (PWCC) circuit is presented. The proposed PWCC technique converting the pulse-width of input clock signal into a modulated output current is applied to improve the conventional sub-sampling phase detector and charge-pump. Implemented by 180 nm CMOS process, the pr...

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关键词

Phase noise,Frequency synthesizers,Phase measurement,Frequency modulation,Power supplies,Very large scale integration,CMOS process

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