Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology
2021 IEEE 34th International System-on-Chip Conference (SOCC)（2021）
摘要
An optimization study of silicon gate-all-around (GAA) devices based on technology computer-aided design tools is presented in this paper. GAA technology guidelines and solutions are provided for low power applications in the 5 nm CMOS technology node. GAA device structure is optimized to achieve maximum electrostatics driven performance. Vertically stacked lateral nanosheet devices display superi...
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关键词
Gate-all-around,stacked nanosheet,footprint,short-channel effect,minimum sized inverter
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