Statistical Estimation of Leakage Power Bounds in CMOS VLSI Circuits

A statistical approach for the estimation of maximum and minimum leakage power in CMOS Very Large Scale Integration (VLSI) circuits is proposed in this paper. The approach is based on the discipline of statistics known as extreme value theory, and incorporates some important recent developments that have appeared in the literature. Experiments upon standard benchmark circuits show that estimates with a relative error of 5% on average (at a 99.99% confidence level) can be easily attained using no more than 3000 input vectors in all occasions.