Carbon Nanotube SRAM in 5-Nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization

Rongmei Chen,Lin Chen,Jie Liang,Yuanqing Cheng,Souhir Elloumi,Jaehyun Lee,Kangwei Xu,Vihar P. Georgiev,Kai Ni,Peter Debacker,Asen Asenov,Aida Todri-Sanial

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2022）

Cited 5|Views22

Key words

CNTFETs,Layout,Integrated circuit interconnections,FinFETs,Metals,SRAM cells,Electrodes,Area,carbon nanotube (CNT) interconnect,carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) array,energy-delay-product (EDP),FinFET SRAM array,layout,read latency,static noise margin,write latency

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