Self-Aligned E-mode GaN p-Channel FinFET with I$_{ON}$ > 100 mA/mm and I$_{ON}$=I$_{OFF}$ > 10$^{7}$

This letter demonstrates self-aligned p-channel FinFETs based on a GaN-on-Si wafer. While the self-aligned gate process helps to achieve shortest possible source-to-drain distance to compensate for low hole mobility in GaN (~20 cm2/V∙s), the FinFET-architecture provides strong electrostatic control over the channel. Our fabricated transistors with 40 nm fin width, LSD = 120 nm and LG = 90 nm exhibits an Ion ≈ 140 mA/mm, Ion/Ioff > 107, VTH = 1 V, SS = 150 mV/dec, gm,max = 14 mS/mm and Ron = 61 Ω∙mm. By precisely controlling the recess depth, enhancement-mode (E-mode) operation was also achieved. Our best E-mode device shows an Ion ≈ 125 mA/mm, Ion/Ioff > 107, VTH = -0.3 V, and Ron = 69 Ω∙mm. In addition, record low subthreshold swing of 80 mV/dec for devices with fin width of 40 nm and LSD = 240 nm attests to the strong gate control over the p-channel achieved by the FinFET-architecture.