A 2.1mW/3.2mW delay-compensated GSM/WCDMA ΣΔ analog-digital converter

Morteza Vadipour,Calvin Chen, A. Yazdi, M. Nariman,Tianwei Li, P. Kilcoyne,Hooman Darabi

symposium on vlsi circuits（2008）

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摘要

A technique to compensate for the harmful excess loop delay in a continuous time SigmaDelta analog-digital converter is presented. With no extra power consumption or area penalty the technique is suitable for variety of applications employing continuous time SigmaDelta analog-digital converters. This work presents a dual mode SigmaDelta ADC for GSM/WCDMA applications with DR of 86 dB/63 dB for 100 KHz/1.92 MHz in a 65 nm CMOS technology with power consumption of 2.1 mW/3.2 mW.

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关键词

CMOS integrated circuits,cellular radio,code division multiple access,sigma-delta modulation,CMOS technology,GSM/WCDMA applications,continuous time SigmaDelta analog-digital converter,delay-compensated GSM/WCDMA SigmaDelta analog-digital converter,dual mode SigmaDelta ADC,frequency 1.92 MHz,frequency 100 kHz,harmful excess loop delay,power 2.1 mW,power 3.2 mW,size 65 nm,

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