A New Screening Method for Alleviating Transient Current Imbalance of Paralleled SiC MOSFETs

Due to material defects and immature process technology, the current level of SiC MOSFET is significantly lower than that of Si IGBT. Connecting multiple chips in parallel has become a common method to increase the current level. The existing chip classification principles are based on the premise that the module or circuit layout is completely symmetrical. However, in practice, it is very difficult for the layout to achieve complete symmetrical parallel branches, especially when many chips are connected in parallel. Therefore, this paper establishes a parallel current sharing model of SiC MOSFETs and proposes a chip screening method considering the influence of mismatched parasitic inductance induced by asymmetric layout of each chips. Finally, the effectiveness of the chip classification method considering the asymmetry of the layout is verified through experiments.