A 16b 120MS/s Pipelined ADC Using an Auxiliary-Capacitor-Based Calibration Technique Achieving 90.5dB SFDR in 0.18 μm CMOS

A 16-bit 120 MS/s sample-hold-amplifier-less(SHA-less) pipelined analog-to-digital converter (ADC) with an on-chip calibration technique in a $0.18~\mu \text{m}$ CMOS process is presented. A switched capacitor circuit with an auxiliary unit capacitor in the multiplying-digital-to-analog converter (MDAC) of the first stage is ...