Baud rate pattern-adaptable dual loop clock recovery for high speed serial links

We present a novel symbol-spaced (baud-rate) clock-and-data recovery (CDR) architecture for high-speed electrical interconnects. Our architecture incorporates two feedback loops operating off of a single 1-bit sampler (slicer), sampling the difference between the incoming data and an offset voltage Vth at the data symbol rate. One loop adapts the Vth and the other loop automa...