10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV V_MIN Reduction With Negligible Active Power Overhead

Zheng Guo,Jami Wiedemer,Yusung Kim, Prithvee S. Ramamoorthy,Prateeksha B. Sathyaprasad,Smita Shridharan,Daeyeon Kim,Eric Karl

IEEE Solid-State Circuits Letters（2021）

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摘要

A 21-Mb/mm ² SRAM design using 0.0367-um ² HCC bitcell on a 10-nm CMOS technology is presented. Gate-modulated selfcollapse (GSC) write-assist is utilized to enable 175 mV VMIN reduction with negligible active energy overhead, and a modest 5.5% array area overhead on a 256-Kb instance. Compared to NBL and TVC write-assist techniques, GSC delivers comparable VMIN improvement across a wide frequency range with 31%-108% write energy reduction.

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关键词

CMOS integrated circuits,semiconductor memory,SRAM,write-assist,write energy

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10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV VMIN Reduction With Negligible Active Power Overhead

10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV V_MIN Reduction With Negligible Active Power Overhead