Edge-Directed LTPS Via Flash Lamp Annealing Using a Cr Adhesion Layer for Improved Wettability

PMOS TFTs built on flash lamp annealed polycrystalline silicon are presented. A thin layer of chromium is used as an adhesion promoter to prevent randomized voids from forming, allowing predictable grain growth in an elongated morphology oriented away from silicon mesa edges. Operational TFTs were realized, revealing that the Cr under-layer does not result in a significant conductance in parallel with the channel, and effectively serves as a barrier to glass contaminants. The methodology supports the production of TFTs with a high degree of electrical uniformity. Comparisons are made between electrical characteristics of transistors with grains oriented in the same direction as the channel carrier pathway versus those with perpendicular orientation; the former demonstrating approximately ten percent higher channel mobility. Process details and representative electrical characteristics are described.