A DPLL-based per core variable frequency clock generator for an eight-core POWER7<sup>&#x2122;</sup> microprocessorJose Tierno,Alexander Rylyakov,Daniel Friedman, Ann Chen, Anthony Ciesla,Timothy Diemoz,George English,David Hui,Keith Jenkins,Paul Muench, Gaurav Rao,George Smith, Michael Sperling,Kevin Stawiasz2010 Symposium on VLSI Circuits（2010）引用 0|浏览0暂无评分AI 理解论文溯源树样例生成溯源树，研究论文发展脉络Chat Paper正在生成论文摘要
