Revisiting PathFinder Routing Algorithm

FPGA(2022)

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摘要
ABSTRACTPathFinder, a popular routing algorithm widely used in the state-of-the-art FPGA compilation tools such as VTR 8, has been reported to have a non-negligible variation in the routing quality under routing resource constraints. Several workaround methods have been proposed to mitigate this undesired effect while keeping the algorithm unchanged. In this paper, we take a fresh look at the PathFinder algorithm itself and identify that its inappropriate definition of routing congestion problems causes an issue in its congestion coefficient updating strategy and eventually leads to the variation in the routing quality under different routing orders. This problem is aggravated in VTR~8 and inevitably degrades the routing quality as the predefined routing order is not optimal in most cases. Based on these findings, we propose an enhanced PathFinder algorithm with redefined routing congestion problems to address the issue in the congestion coefficient updating strategy and algorithmically resolve the routing quality variation issue. This enhanced algorithm can be easily integrated into VTR~8 to benefit every researcher in our community. Evaluation results show that it reduces the longest critical path delay and the variation by up to 49.4% and 96.2% under routing resource constraints, respectively. The variation can be fully eliminated when sufficient routing iterations are performed.
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