Accelerate SAT-based ATPG via Preprocessing and New Conflict Management Heuristics

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)(2022)

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摘要
Due to the continuous advancement of semicon-ductor technologies, there are more defects than ever widely distributed in manufactured chips. In order to meet the high product quality and low defective-parts-per-million (DPPM) goals, Boolean Satisfiability (SAT) technique has been shown to be a robust alternative to conventional APTG techniques, especially for hard-to-detect faults. However, the SA...
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关键词
Runtime,Databases,Transforms,Product design,Topology,Quality assessment,Circuit faults
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