A radiation-hardened 14T SRAM cell for highly reliable space application

A 14T SRAM bit-cell, implemented in 130-nm CMOS technology, with excellent read stability and soft error tolerance performance has been proposed. The parasitic extracted simulations show that compared with considered memory cells, the proposed cell achieves up to 146% read access time saving at the cost of acceptable layout area and leakage power dissipation overhead. The RSNM of 14T bit-cell is about x2.6 that of DICE structure, revealing excellent read stability. In addition, the proposed cell provides larger the critical charge, which indicates more superior soft error resilience ability.