DAC Bandwidth Tripler with 3:1 Image-Rejection Analog Multiplexer

This paper proposes a DAC bandwidth tripler with a 3:1 image-rejection analog multiplexer used for low, middle, and high band. This technique enables bandwidth extension of three times and keep high accuracy of signals without complicated signal processing for distortion compensation. In addition, excellent potential of the proposed tripler will be presented by computer simulation using PAM4 signal and 0.18 mu m n-MOSFETs. The tripler showed high accuracy with an EVM of -35.3 dB at 10 Msymbol/ s without distortion compensation. In addition, the tripler demonstrates eye opening up to 10 Gsymbol/s.