Improved MEOL and BEOL Parasitic-Aware Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet Transistor

In this article, an improved parasitic-aware design technology co-optimization (DTCO) for gate-all-around nanosheet field effect transistor (GAA-NSFET) at 3 nm node is proposed. The presented DTCO flow owns two distinct features. First, a novel de-embedding strategy is designed to avoid the repeated calculation of gate–source/drain contact capacitance. Second, the parasitic resistance of the middl...