High density V-GAA transistor structure array based on self-aligned double patterning

In this work, the pillar structure of V-GAA transistor has been developed for sub 10 nm technology node application in DRAM. SADP method with 193 nm wavelength was used to define the pitch of 41 nm along the word line direction and that of 47.3 nm along the bit line direction. The pillar structure was observed by TEM. The VGAA transistor pillar array density is as high as ~517 Mb/mm2.