Modeling and Analysis of System-Level Power Supply Noise Induced Jitter (PSIJ) for 4 Gbps High Bandwidth Memory (HBM) I/O Interface

Taein Shin,Hyunwook Park,Keunwoo Kim,Seongguk Kim,Keeyoung Son,Kyungjune Son,Gapyeol Park,Joonsang Park,Seonguk Choi,Joungho Kim

2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)（2021）

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摘要

In this paper, for the first time, we model and analyze the impacts of parallel I/O interface factors on system-level power supply noise induced jitter (PSIJ) in 4 Gbps HBM. PSIJ is positioned as an important noise component that determines the overall chip-packaging operations. To predict the accurate PSIJ, it must be evaluated at system-level with different domains including chip domain, SI/PI d...

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关键词

Analytical models,Power supplies,Frequency-domain analysis,Bandwidth,Jitter,Packaging,Integrated design

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