Systematic Application of UCIS to Improve the Automation on Verification Closure

Interoperability between verification flows and tools is of particular importance for verification engineers and the EDA industry. While UVM and the Unified Coverage Interoperability Standard (UCIS) target the unified creation and reuse of verification environments, the flow from verification plan to testbench implementation and extraction of coverage data is still a time-consuming and error prone task, for which little automation support is available. In this article we present how to implement a coverage plan-driven functional coverage metric generation for SystemC verification environments, by means of UCIS and stateof-the art code generation and Model-driven Engineering (MDE) techniques.