Performance Counter Design Variation in Rocket Chip via Feature-Oriented Programming

Performance counters provide critical information to developers about how well their applications work on a given platform. Currently, the Rocket Chip generator includes a performance counter system that allows variation only of the number of counting registers. For RISC-V to be attractive across a wide range of applications, other variations should be possible. For example, a developer may be interested only in microarchitecture events. Perhaps the events of interest may yield more information if counted only within a specific function. We reformulate the performance counter subsystem into separate and orthogonal feature units that can be applied to Rocket Chip either individually or in combination. We developed a tool that applies features by manipulating Scala abstract syntax trees and automatically determines feature dependencies. We also designed a simple domain specific language to construct such features. By feature-orienting the implementation of the performance counters, we offer Rocket Chip developers a much larger range of possible implementations. Developers can select any subset of RISC-V events for monitoring. New events can be easily introduced into attached processors for monitoring. If desired, events can be counted only within certain ranges of the program counter. We reconstruct the current performance counters using our features as well as other interesting design endpoints. We present results showing the resources needed for those configurations.