Improving Ge-rich GST ePCM reliability through BEOL engineering

A. Redaelli, A. Gandolfo, G. Samanni, E. Gomiero,E. Petroni, L. Scotti, A. Lippiello,P. Mattavelli, J. Jasse, D. Codegoni,A. Serafini,R. Ranica,C. Boccaccio, J. Sandrini,R. Berthelon,JC. Grenier,O. Weber, D. Turgis, A. Valery,S. Del Medico, V. Caubet,JP. Reynard,D. Dutartre,L. Favennec,A. Conte, F. Disegni,M. De Tomasi, A. Ventre,M. Baldo,D. Ielmini,A. Maurelli,P. Ferreira,F. Arnaud,F. Piazza,P. Cappelletti, R. Annunziata, R. Gonella

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)（2021）

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摘要

This paper discusses the effect of back-end of line (BEOL) process on cell performance for a Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM). The impact of BEOL is first shown by describing the microscopic evolution of the active Ge-rich GST alloy during process. Ge clustering has been proven to occur during the fabrication process, impacting the pristine resistance and the after for...

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关键词

Resistance,Performance evaluation,Microscopy,Memory management,Europe,Reliability engineering,Germanium

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