Channel Stress Engineering Through Source/Drain Recess Optimization and Its Process Variation Study for 5 nm-node FinFETs.

In this paper, we present a simulation study of channel stress based on the 5 nm FinFET structure. Different source/drain recess schemes have been comprehensively investigated. With the source/drain ‘Dry+Wet’ recess, up to 70% channel stress enhancement has been achieved due to larger epitaxy volume and closer stressor-to-channel distance. Furthermore, the geometry dependences of different source/drain recess schemes have also been discussed, showing that the ‘Dry+Wet’ recess scheme significantly reduces the channel stress variation caused by the Fin width deviation from 23% to 5%. However, other dimensions along the Fin direction have obvious impacts on the channel stress for different recess schemes. And this stress variation should be taken carefully in circuit and layout design.