Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS.

With the development of computing-in-memory (CIM) in machine learning (ML) technology, we need higher precision to improve the performance of neural networks (NN). However, analog-to-digital converter (ADC) area and power consumption occupy a large part of the whole chip. This work presents an energy-efficient successive-approximation-register (SAR) ADC to diminish the power problem in CIM without destroying the initial NN structure. Firstly, we propose a configurable SAR ADC with various operating thresholds to deal with different precision of weight including 4-bit weight and high precision weight. Secondly, a circuit-algorithm co-design scheme program the operating mode and cycle of the bit line in ADC to improve energy utilization. The prototype in 28 nm CMOS technology occupies 871.22 um ² . It consumes 37.88uW from a 0.9V supply at 50MHz. The energy efficiency of ADC in CIM can be increased at most 20.72% ~ 40.44%.