A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC

The paper presents a 5-bit high-linearity, binary-recombination-redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC in TSMC 28nm process. The highlight of the paper is the proposed high-linearity Sub-SAR ADC using binary recombination redundancy technique with high-speed SAR logic. In addition, the proposed high-speed SAR logic is energy-efficient. In this paper, the requirement proposed b...