HV ESD Device Solution Evaluations in 55nm BCD Technology

Sagar P Karalkar,Milova Paul, Xiao Mei Elaine Low,Kyong Jin Hwang,Robert Gauthier

2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)（2021）

引用 2|浏览0

暂无评分

摘要

Effective High-Voltage (HV) ESD (Electrostatic Discharge) solutions for 12V power pad protection in 55nm BCDLite® were studied in this paper. A comparison between different types of devices, gate-grounded NMOS (GGNMOS), PNP, and NPN for HV ESD protection with key performance metrics were studied.

查看译文

关键词

Performance evaluation,Integrated circuits,Costs,Failure analysis,Voltage,Logic gates,Robustness

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要