A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS

Hong-Seok Choi,Seungha Roh,Sanghee Lee, Jung-Hoon Park,Kwanghoon Lee,Youngha Hwang,Deog-Kyoon Jeong

2021 18th International SoC Design Conference (ISOCC)（2021）

引用 1|浏览0

暂无评分

摘要

This brief presents a 32-way 6b 48-GS/s asynchronous time-interleaved ADC. To enhance sub-ADC conversion speed, 2b/cycle asynchronous SAR ADC is adopted for sub-ADC structure, which can operate at 1.5-GHz. Instead of using reference DAC, 9 built-in reference samplers are employed for 6b 2b/cycle operation. Interleaver incorporates 8 sample and hold amplifiers (SHA) and each SHA drives 4 sub-ADCs. ...

查看译文

关键词

Power demand,Linearity,CMOS process,Timing,Analog-digital conversion,Clocks

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要