PROCESSORS, METHODS AND SYSTEMS WITH A CONFIGURABLE ROOM ACCELERATOR

Systems, methods and apparatus relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a synchronizer circuit coupled between a first tile interconnect network and a second tile interconnect network and including memory for storing the data to be sent between the first tile interconnect network and the second tile interconnect network wherein the synchronizer circuit converts the data from the memory between a first voltage or a first frequency of the first tile and a second voltage or frequency of the second tile to generate converted data and the converted data between the interconnection network of the first tile and the interconnect network of the second tile.