Parallelized Technology Mapping to General PLBs by Adaptive Circuit Partitioning

Technology mapping from logic netlists to programmable logic blocks (PLB) plays an important role in FPGA EDA flow, especially for architecture exploration of PLBs. However, technology mapping becomes time-consuming due to the booming scale and complexity of IC designs as well as the growing complexity of PLB architectures. To speed up this process, a parallelized technology mapping approach based...