DLBF: A low overhead wear leveling algorithm for embedded systems with hybrid memory

Due to its attractive characters, nanosecond ranged access latency and higher bit density，phase change memory (PCM) has emerged as a promising main memory candidate for embedded systems in the future. However, relatively lower endurance has limited its practical application. Discussions regarding hybrid memory wear leveling algorithms have dominated research dereliction in recent years. However, most previous wear leveling schemes could not predict the write and read hot pages accurately and always greatly depend on reference-count recording lists to predict the hot of the pages which would bring higher space overhead to the whole system.