Statistical Analysis Of The Impact Of 2d Reticle Variability On Wafer Variability In Advanced Euv Nodes Using Large-Scale Monte Carlo Simulations

In this submission we describe a framework to simulate mask variability in the form of CD distributions, edge placement error distributions and edge roughness. The impact of each method on wafer variability is then simulated. The results show that assumptions of mask edge placement correlation affect the match of simulated wafer variability to experiment, and that simulated mask contributions to wafer variability are not negligible. The authors demonstrate that for a DRAM use case, wafer level variability increases with scaling, but can be reduced with mask and wafer process improvement. For a curvilinear use case it is demonstrated that the contribution of mask roughness to wafer level variation can be large compared to typical process specs.