Single-poly Floating-Gate Memory Cell Options for Analog Neural Networks

In this paper, we explore the use of a 180 nm CMOS single-poly technology platform for realizing analog Deep Neural Network integrated circuits. The analysis focuses on analog vector-matrix multiplier architectures, one of the main building blocks of a neural network, implementing in-memory computation using Floating-Gate multilevel non-volatile memories. We present two memory options, suited either for current-mode or for time-domain vector-matrix multiplier implementations, with low-voltage charge-injection program and erase operations. The effects of a limited accuracy are also investigated through system-level simulations, by accounting for the temperature dependence of the stored weights and the corresponding impact on the network error rate.