Temperature Assessment Of Si1-Xgex Source/Drain Heterojunction Nt-Jlfet For Gate Induced Drain Leakage - A Compact Model

In this paper, we have investigated the impact of temperature (T) and drain bias voltage (V-ds) on gate induced drain leakage (GIDL) in SiGe Source/Drain heterojunction silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET). We developed a temperature dependent model for surface potential, electric field E-Z, L-BTBT induced I-GIDL and full drain current I-ds using 2-D Poison equation with suitable boundary conditions. We have also examined impact of temperature (activation energy) and drain bias voltage (electric field) on L-BTBT induced I-GIDL. It is found that the increase in drain bias voltage causes 31.1% rise in IGIDL and elevation in temperature has 29.4% increase in I-GIDL. Furthermore, we have examined impact of temperature on transconductance (g(m)) and output conductance (g(d)). The results demonstrated that temperature and drain bias voltage has significant impact on SiGe S/D NTJLFET, however, it is considerably less than the NTJLFET.