Novel Si/Sige Fin On Insulator Fabrication On Bulk-Si Substrate

In this paper, novel Si/SiGe fin on insulator (FOI) structure fabrication on bulk-Si substrate is systematically explored. A notched Si/SiGe fin etching is first achieved by using a novel three-step etching after a high-quality of SiGe layer epitaxially grown is realized on a Si substrate by optimizing the epitaxial process. To fabricate the Si/SiGe FOI structure, isolation of upper Si/SiGe fin above the notch is investigated by a direct rapid thermal anneal (RTA) oxidation scheme, spike anneal post SiGe fin reveal scheme, and SiN spacer protection scheme. It is found that all these three schemes can achieve the upper Si/SiGe isolation at the notch location, but the direct RTA oxidation scheme suffers the issue of serious oxidation of SiGe fin because SiGe is more easily oxidized than Si in O-2 ambient. Furthermore, compared with the direct oxidation scheme, the spike anneal post SiGe fin reveal scheme can attain an obvious better SiGe fin profile. However, there is still a minor lateral loss of SiGe fin caused by the oxidation of SiGe fin due to the residual O-2 in N-2 ambient. The SiN film covering the revealed SiGe fin before spike anneal treatment may be an effective solution to avoid the oxidation of SiGe fin. Meanwhile, SiN spacer protection scheme by employing a SiN spacer post the step-I etching of the three-step etching can realize the Si/SiGe FOI structure and protect the upper SiGe fin from oxidation during the low-temperature RTA oxidation process. Therefore, using the SiN film or spacer to protect SiGe from oxidation is a necessary way to fabricate the Si/SiGe FOI structure. Meanwhile, the SiN spacer protection scheme with a relative low temperature RTA isolation oxidation is a prefer choice compared with the spike anneal post SiGe fin reveal scheme.