Thermal And Electrical Performance For Stack Chip Package

To apply a kind of high-density memory solution, especially for workstation and PC server, a stack chips package (referred to as "SCP" hereafter) has been developed. The SCP contains a plurality of both memory chips and lead frames serving as an interposer within a molded plastic package. Each chip is selected in an alternative manner, resulting in the package with a memory capacity twice that of monolithic chip. The plural lead frames are electrically interconnected all at once, using metal solders electroplated on the lead frame surface.The thermal performance of SCP was evaluated by means of a thermal model utilizing Finite Element Method (FEM)[1]. The thermal model used the non-linear boundary conditions involving temperature dependent convection and radiation effect. The model was verified for 128M. SCP that inserted two real 64M SDRAM and shown to be in good agreement within average 10% deviation. The FEM results show the good thermal performance of SCP - in detail that the theta JA of 128M SCP increase to only 5% than 64M SDRAM TSOP in real operation conditions.The AC/DC electrical performance of 128M SCP was investigated under various ambient temperatures. The access time was increased maximum 0.3 nsec and the minimum VDD voltage that could make the access time be 6 nsec was shifted by approximately 0.1V compared to 64M SDRAM TSOP at the tested temperature range.