A 7nm 4ghz Arm (R)-Core-Based Cowos (R) Chiplet Design For High Performance Computing

A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS (R)) was implemented in 7nm 15M process. Each SoC chiplet has four Arm (R) Cortex (R)-A72 processors operating at 4GHz. The on-die interconnect mesh bus operates above 4GHz at 2mm distance. The inter-chiplet connection features a scalable, 0.56pJ/bit power efficiency, 1.6Tb/s/mm(2) bandwidth density, and 0.3V Low-voltage-In-Package-INterCONnect (LIPINCON (TM)) interface achieving 8Gb/s/pin and 320GB/s bandwidth. Silicon test-chip measurements validate the processor, on-die interconnects and inter-chiplet interface performance. The built-in eye-scan feature shows the inter-chiplet connection achieves 244mV eye-height and 69% UI eye-width.