Trigate 6t Sram Scaling To 0.06 Mu M(2)

M. Guillorn,J. Chang,A. Pyzyna, S. Engelmann, E. Joseph, B. Fletcher, C. Cabral,C. -H. Lin,A. Bryant, M. Damon, J. Ott, C. Lavoie, M. Frank, L. Gignac,J. Newbury,C. Wang,D. Klaus, E. Kratschmer, J. Bucchignano, B. To, W. Graham, I. Lauer, E. Sikorski, S. Carter,V. Narayanan, N. Fuller,Y. Zhang,W. Haensch

2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING（2009）

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摘要

We present an aggressively scaled trigate device architecture with undoped channels, high-kappa gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 mu m(2). This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated with planar devices [1].

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