Energy-Efficient 32 X 32-Bit Multiplier In Tunable Near-Zero Threshold Cmos

An 80,000 transistor, law swing, 32 x 32-bit multiplier nas fabricated in a standard 0.35 mu m, V-th=0.5 V CMOS process and in a 0.35 pm, back-bias tunable, near-zero Vtr, process. While standard CMOS at V-dd=3.3 V runs at 136 MHz, the same performance can be achieved in the low-V-th version at V-dd=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained far frequencies down to 10 MHz. In addition, the low-V-th version is able to run at 188 MHz, which is 38% faster than standard CMOS.